[1] M. Wachs, O. Sacham, Z.
Asgar, A. Firoozshahian, S. Richardson, M. Horowitz, “Bringing Up a Chip on the Cheap,”
IEEE Design and Test of Computers, Volume 29, Issue 6, Dec. 2012 pp 57-65. (PDF)
[2] O. Sacham, O. Azizi, M.
Wachs, W. Qadeer, A. Asgar, K. Kelley, J.P. Stevenson, S. Richardson, M.
Horowitz, B. Lee, A. Solomatnikov, A. Firoozshahian, “Rethinking Digital Design:
Why Design Must Change,” IEEE Micro, Volume
30, Issue 6, Nov.-Dec. 2010 PP 9-24 (Invited Paper). (PDF)
[3] J. Leverich, H. Arakida,
A. Solomatnikov, A. Firoozshahian, M. Horowitz, C. Kozyrakis, “Comparative
Evaluation of Memory Models for Chip Multi-Processors,”
ACM Transactions on Architecture and Code Optimization (TACO), Volume 5,
Issue 3, Article 12, Nov. 2008. (PDF)
[4] Gh. Miremadi, B. Salamat,
A. Firoozshahian, “Design and Implementation of a System for
Microprocessor Laboratory," Proceedings of Sharif
University of Technology, 1998-1999, pp 157-166.
[1] Amin Firoozshahian, Joel
Coburn, Roman Levenstein, Rakesh Nattoji, Ashwin Kamath, Olivia Wu, Gurdeepak
Grewal, Harish Aepala, Bhasker Jakka, Bob Dreyer, Adam Hutchin, Utku Diril,
Krishnakumar Nair, Ehsan K. Aredestani, Martin Schatz, Yuchen Hao, Rakesh Komuravelli,
Kunming Ho, Sameer Abu Asal, Joe Shajrawi, Kevin Quinn, Nagesh Sreedhara,
Pankaj Kansal, Willie Wei, Dheepak Jayaraman, Linda Cheng, Pritam Chopda, Eric
Wang, Ajay Bikumandla, Arun Karthik Sengottuvel, Krishna Thottempudi, Ashwin
Narasimha, Brian Dodds, Cao Gao, Jiyuan Zhang, Mohammed Al-Sanabani, Ana
Zehtabioskuie, Jordan Fix, Hangchen Yu, Richard Li, Kaustubh Gondkar, Jack
Montgomery, Mike Tsai, Saritha Dwarakapuram, Sanjay Desai, Nili Avidan,
Poorvaja Ramani, Karthik Narayanan, Ajit Mathews, Sethu Gopal, Maxim Naumov,
Vijay Rao, Krishna Noru, Harikrishna Reddy, Prahlad Venkatapuram, Alexis
Bjorlin, “MTIA: First
Generation Silicon Targeting Meta's Recommendation Systems,” Proceedings of
the 50th Annual International Symposium on Computer Architecture (ISCA ’23),
June 17-21, 2023, Orlando, FL. (PDF)
[2] L. Ke, U. Gupta, B. Y.
Cho, D. Brooks, V. Chandra, U. Diril, A. Firoozshahian, K. Hazelwood, B. Jia,
H.S. Lee, M. Li, B. Maher, D. Mudigere, M. Naumov, M. Schatz, M. Smelyanskiy,
X. Wang, B. Reagen, C.J. Wu, M. Hempstead, X. Zhang, “RecNMP: Accelerating
Personalized Recommendation with Near-Memory Processing,” Proceedings of
the 47th Annual International Symposium on Computer Architecture
(ISCA ’20), May 30th – June 3rd 2020, Valencia, Spain,
pp. 790-803. (PDF)
[3] S. Ghorbani, Z. Yang,
P.B. Godfrey, Y. Ganjali and A. Firoozshahian, “DRILL: Micro Load
Balancing for Low-Latency Data Center Networks,” Proceedings of the
Conference of the ACM Special Interest Group on Data Communication (SIGCOMM
’17), Aug. 21-25, 2017, Los Angeles, CA, pp. 225-238. (PDF)
[4] S. Ghorbani, B. Godfrey,
Y. Ganjali and A. Firoozshahian, “Micro Load Balancing in Data
Centers with DRILL”, Proceedings of the 14th ACM Workshop on Hot Topics
in Networks (HotNets XIV), Nov. 16-17, 2015, Philadelphia, PA, Article no. 17.
(PDF)
[5] H. Litz, D. Cheriton, A.
Firoozshahian, O. Azizi, J.P. Stevenson, “SI-TM:
Improving Transactional Memory Abort Rates through Snapshot Isolation,” Proceedings of the 19th International
Conference on Architectural Support for Programming Languages and Operating
Systems (ASPLOS ’14), Mar. 01-05, 2014, Salt Lake City, UT, pp. 383-398. (PDF)
[6] J.P. Stevenson, A.
Firoozshahian, A. Solomatnikov, M. Horowitz, D. Cheriton, “Sparse Matrix-Vector Multiply on HICAMP Architecture,” Proceedings of the 26th International
Conference on Supercomputing (ICS ‘12), Jun. 25-29, 2012, Venice, Italy, pp.
195-204 (Winner of the Best Paper Award). (PDF)
[7] D. Cheriton, A.
Firoozshahian, A. Solomatnikov, J.P. Stevenson, O. Azizi, “HICAMP: Architectural Support for Efficient Concurrency-Safe
Shared Structured Data Access,” Proceedings of the
17th International Conference on Architectural Support for
Programming Languages and Operating Systems (ASPLOS XVII), Mar. 03-07, 2012,
London, England, pp. 287-300. (PDF)
[8] A. Solomatnikov,
A. Firoozshahian, O. Shacham, Z. Asgar, M. Wachs, W. Qadeer, S. Richardson, M.
Horowitz, “Using a
Configurable Processor Generator for Computer Architecture Prototyping,” Proceedings of the
42nd International Symposium on Microarchitecture (MICRO
42), Dec. 12-16, 2009, New York, NY, pp. 358-369. (PDF)
[9] A.
Firoozshahian, A. Solomatnikov, O. Shacham, Z. Asgar, S. Richardson, C.
Kozyrakis, M. Horowitz, “A Memory System Design Framework: Creating Smart
Memories,” Proceedings of
the 36th
International Symposium on Computer Architecture (ISCA ‘09), June. 20-24, 2009,
Austin, TX, pp. 406-417. (PDF)
[10] O.
Shacahm, M. Wachs, A. Solomatnikov, A. Firoozshahian, S., Richardson, M.
Horowitz, “Verification
of Chip Multiprocessors Memory Systems Using a Relaxed Scoreboard,” Proceedings of
the 41st International Symposium on Microarchitecture (MICRO 41),
Nov. 08-12, 2008, Lake Como, Italy, pp. 294-305. (PDF)
[11] J.
Leverich, H. Arakida, A. Solomatnikov, A. Firoozshahian, M. Horowitz, C.
Kozyrakis, “Comparing
Memory Systems for Chip Multi-Processors,” Proceedings of the
34th International Symposium on Computer Architecture
(ISCA ‘07), Jun. 09-13, 2007, San Diego, CA, pp. 358-368. (PDF)
[12] A.
Firoozshahian, V. Manshadi, A. Goel, B. Prabhakar, “Efficient,
Fully Local Algorithm for CIOQ Switches,” Proceedings of
the 26th Annual IEEE Conference on Computer Communications (INFOCOM
2007), May. 06-12, 2007, Barcelona, Spain. (PDF)
[13] A.
Solomatnikov, A. Firoozshahian, W. Qadeer, O, Shacham, K, Kelley, Z. Asgar, M.
Wachs, R. Hameed, M. Horowitz, “Chip Multi-Processor Generator,” Proceedings of the 44th Design Automation
Conference (DAC ‘07), Jun. 04-08, 2007, San Diego, CA, pp. 262-263. (PDF)
[14] A.
Solomatnikov, A. Firoozshahian, F. Labonte, M. Horowitz, C. Kozyrakis, K.
Olukotun, K. Mai, “Smart
Memories: A Configurable Processor Architecture for High Productivity Parallel
Programming,” Government
Microcircuit Applications and Critical Technology Conference (GOMACTech 2005),
Apr. 04-07, 2005, Las Vegas, NV. (PDF)
[15] A. Firoozshahian, Z. Navabi, M. Kamarei,
“Behavioral Simulation of Bluetooth Transceiver and Radio Channel
Using VHDL,” Proceedings of the 4th Iranian
Student Conference on Electrical Engineering (ISCEE), Faculty of Engineering,
University of Tehran, September 2001. (PDF)
S. Ghorbani Khaledi, Y.
Ganjali, A. Firoozshahian, “Using Memory and Random Sampling for Load
Balancing in High-radix Switches,” University of Toronto SNL Technical
Report TR10-SN-UT-07-10-21. (PDF)
[1]
M. Schatz, A. Firoozshahian, “Distributed Physical Processing of Matrix Sum Operation,”
United States Patent, No. 20210042116 A1.
[2]
M. R. Haghighat, K Doshi, A.J. Herdrich, A. Mohan, R.R. Iyer, M. Sun, K.
Bhuyan, T.J. Goh, M.J. Kumar, M. Prinke, M. Lemay, L. Peled, J. Tsai, D.M.
Durham, J. D. Chamberlain, V.A. Sukhomlinov, E.J. Dahlen, S. Baghsorkhi, H.
Sane, A. Melik-Adamyan, R. Sahita, D.Y. Babokin, I.M. Steiner, A. Bachmutsky,
A. Rao, M. Zhang, N.K. Jain. A. Firoozshahian, B.V. Patel, W. Huang, Y. Raghuram,
“Function as a Service (FaaS) System Enhancements,”
International Patent, No. WO2020096639 A1.
[3]
F. Guim Bernart, K. Kumar, M. Hajeer, T. Willhalm, A. Firoozshahian, C. Egbert,
“Concept for Approximate Deduplication in Storage and Memory,” United
States Patent, No. 20190121564 A1 (Pending).
[4]
I. Agarwal, O. Azizi, C. Egbert, A. Firoozshahian, D.C. Hansen, A. Kleen, M.
Maddury, M. Madhav, A. Raj, A. Solomatnikov, S. Van Doren, “Memory Pressure Notifier,” United States Patent,
No. 20190196988 A1.
[5]
O. Azizi, A. Firoozshahian, J. Stevenson, M. Maddury, C. Egbert, H. Neefs, “Lazy Memory Deduplication,” United States Patent,
No. 20190212935 A1.
[6]
O. Azizi, A. Firoozshahian, A. Kleen, M. Madhav, M. Maddury, C. Egbert, E.
Gouldy, “Reservation Architecture for Overcommitted Memory,”
United States Patent, No. 20190213120 A1.
[7]
V. Bahirji, A. Firoozshahian, M. Madhav, T. Opferman, O. Azizi, “Physical Page Tracking for Handling Overcommitted Memory,”
United States Patent, No. 20190354487 A1.
[8] A.
Firoozshahian, G. Vedaraman, A. Kleen, S. Van Doren, O. Azizi, M. Madhav, M.
Maddury, C. Egbert, “Survivability Guarantees for Memory Traffic,”
European Patent, No. EP3547150B1.
[9] D.
Cheriton, A. Firoozshahian, A. Solomatnikov, “Iterator Register for Structured Memory,” Unites
States Patent, No. 20170249992 A1.
A. Firoozshahian, “Smart
Memories: A Reconfigurable Memory System Architecture,” Ph.D.
Dissertation, Electrical Engineering Department, Stanford University, 2009. (PDF)
O. Shacham, Z. Asgar, H. Chen, A.
Firoozshahian, R. Hameed, C. Kozyrakis, W. Qadeer, S. Richardson, A.
Solomatnikov, D. Stark, M. Wachs, M. Horowitz, “Smart Memories
Polymorphic Chip Multiprocessor,” DAC/ISSCC Student Design Contest, 46th
Design Automation Conference (DAC 46), San Francisco, CA, 2009 (Winner of the first prize).
(PDF)